Using just two NAND or inverter gates its possible to build a D type (or ‘toggle’) flip-flop with a push-button input. At power-up the output of gate N2 is at a logical ‘1’, ensuring that transistor T2 ...

首先考虑NMOS部分，如果其中一个NMOS门是高电平，输出必须保持低电平。如下图所示。 其次， PMOS部分，如果A为高，B为高，或者A、B均为高时，PMOS部分必须处于关断的状态。而且，如果A和B均为低时，PMOS部分必须为ON的状态。 如下图所示，即满足以上的要求。

Any typical digital design style with CMOS uses complementary pairs of p-type and n-type MOSFETs for logic functions implementation. Naturally, CMOS always ought to provide INVERTED outputs like ...

The 74ABT00 is a quad 2-input NAND gate. This device is fully specified for partial power down applications using Ioff. The Ioff circuitry disables the output, preventing the potentially damaging ...