New research paper titled “Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification” from researchers at University of Bristol and Infineon Technologies. “Constrained ...

As chips become more heterogeneous with more integrated functionality, testing them presents increasing challenges — particularly for high-speed system-on-chip (SoC) designs with limited test pin ...

BOULDER, Colo.--(BUSINESS WIRE)--Biodesix, Inc. (Nasdaq: BDSX), a leading data-driven diagnostic solutions company with a focus in lung disease, today announced that the United States Patent and ...

Scan is a structured test approach in which the overall function of an integrated circuit (IC) is broken into smaller structures and tested individually. Every state element (D flip-flop or latch) is ...

One of the recurring themes in this column over the past few years has been the development of new test methods for sandwich composites. This is primarily a result of the opportunities I’ve had to ...